C.R.Y.O. asks:
I’m a recruiter working in the high-tech industry. A contact at a large research institute wants to build a team of 30-50 engineers specialized in back-end technology, specifically CoWos. Ideally, we’d acquire a small company or have these specialists join our payroll.
It’s the technology of the future, or so I’ve been told. I have ten years of experience in recruitment, but this is entirely new to me. How should I approach this? Could you help get us started? Do you know of companies that operate in this technological space?
The headhunter answers:
The research institute you work for likely knows all the companies involved in back-end technologies. Chip-on-wafer-on-substrate, or Cowos, is a packaging technique in which multiple chips are placed directly onto a wafer and then mounted onto a substrate. This specific 2.5D and 3D advanced packaging technology was developed by TSMC. Therefore, you’ll primarily find specialists there.
TSMC’s foundry competitors, Intel and Samsung, have developed their own technically equivalent alternatives. There are also OSATs working on high-end advanced packaging. Due to Cowos capacity shortages at TSMC, these companies collaborate closely with TSMC.
Aside from fabs, design and IP houses play a crucial role. Firms like Faraday, Alchip and Broadcom develop the interconnect IP and help fabless companies physically prepare their chip designs for Cowos or equivalent production. Because the market for chiplet architecture is growing rapidly, a specific layer of companies has emerged that designs the ‘glue’ to enable heterogeneous integration.
These design and IP houses are divided into several segments. The IP giants possess the crucial building blocks required to enable chiplets to communicate at high speeds. Think of Synopsys and Cadence, which provide the complete EDA toolchains that engineers use to design a 2.5D or 3D chip. Alphawave Semi is a specialist in high-speed connectivity. They focus on energy-efficient chiplet-to-chiplet interfaces and deliver complete subsystems for AI chips. Finally, there’s Rambus, known for their expertise in memory architecture. They develop the specific IP interfaces for high-bandwidth memory (HBM), an essential component of almost any Cowos design.
The next sub-category consists of specialized ASIC design houses, also known as value chain aggregators (VCAs). These companies often don’t design their own chips but instead translate a client’s concept into a physical design that’s ready for the fabs of TSMC, Intel or Samsung. GUC is a highly important player here because TSMC holds a large stake in the company, and it serves as their regular partner for advanced packaging. Then there’s Marvell Technology, which functions as a high-end custom ASIC partner, alongside players like Sondrel and Verisilicon. The latter operates on a “Silicon Platform as a Service” model and has extensive experience integrating third-party IP into advanced packages.
The final sub-category comprises the pure-play chiplet IP companies. In the slipstream of the chiplet revolution, they focus purely on the challenges of heterogeneous integration. Think of Eliyan, Blue Cheetah Analog Design and Dreambig Semiconductor.
If I were you, I’d dive into this ecosystem first and then sit down with your client to determine their exact needs. It would be useful to get more specific information about what they’re actually looking for. Be sure to ask about the budget as well, because you only have to check the financial pages to know that high-end talent like this doesn’t come cheap.