Job description

As a Senior Mixed-signal Verification Engineer you will actively participate in the definition and implementation of our verification solutions. You will be responsible to verify our SoCs, IPs and modules of wireless connectivity systems and products. These responsibilities include:

  • Working within the multidisciplinary team to verify the functionality and performance of our IP blocks and SoCs for wireless connectivity components and systems;
  • Read, analyze and provide feedback relating to the verification aspects of the new projects and IP’s to be developed;
  • Interact with the design and validation teams to define the verification procedure and requirements;
  • Define and drive the system level verification plan. Drive the implementation of test-benches and stimuli generation according to the verification plan;
  • Implement behavioral models and verification environments/ routines/ classes/ components/ etc.;
  • Run simulations, analyze results and prepare reports to be discussed with the design team;
  • For each phase of verification, report and communicate proactively about the status, the risks and issues;
  • Investigate for new methods and techniques of functional verification on both theoretical and practical levels.



  • Excellent understanding of functional verification principles, concepts, and challenges;
  • Professional industrial involvement in the field of semiconductor and microelectronics for at least 5 years;
  • Proven experience with simulating and debugging complex software systems;
  • Passionate about verification rather than design;
  • Out of the box thinker and having the required creativity to address verification challenges and issues;
  • Quick learner eager to learn and develop constantly, open mind, excellent communicator and capability to initiate and drive new activities;
  • Good knowledge of analog/RF circuits, digital and embedded systems;
  • Good knowledge and understanding of the principles of communication systems and protocols;
  • Knowledge of verification platforms like Mentor Questa and Cadence NCSim.
  • Good experience with scripting languages like Tcl, Perl, etc.;
  • Ability to work with Simulink and MATLAB would be a huge plus;
  • Experience in C, SystemVerilog, and UVM would be huge plus;
  • Very good technical documentation and specification skills.



Please contact Anton van Rossum on +31-6-53-306-309 or anton@ir-search.nl.

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